The following features are emulated:
- 5a22 CPU core (bus-cycle accurate)
- Memory access timing
- SA-1 -> S-CPU interrupts (IRQ + CHDMA IRQ)
- S-CPU -> SA-1 interrupts (IRQ + Timer IRQ + DMA IRQ + NMI)
- SIV / SNV interrupt vector selection
- Timer unit (linear and H/V)
- Super MMC unit (ROM + BW-RAM)
- BS-X flash cart slot mapping
- Normal DMA
- Character-conversion 1 DMA (2bpp + 4bpp + 8bpp)
- Character-conversion 2 DMA (2bpp + 4bpp + 8bpp)
- BW-RAM virtual bitmap mode (2bpp + 4bpp)
- Arithmetic unit (multiplication + division + cumulative sum)
- Variable-length bit processing (fixed and auto increment)
While the following features are not currently emulated, mostly due to lack of information:
- SA-1 bus conflict delays
- Write protection (BW-RAM + I-RAM)
- SA-1 CPU priority for DMA transfers
- DMA access timing
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